摘要 :
Incremental methods are successfully applied to deal with successive verifications of slightly modified switch-level networks. That is, only those parts affected by the changes are symbolically traversed for verification. In this ...
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Incremental methods are successfully applied to deal with successive verifications of slightly modified switch-level networks. That is, only those parts affected by the changes are symbolically traversed for verification. In this paper, we present an incremental technique for symbolic simulators which is inspired in both existing incremental techniques for non-symbolic simulators and a token-passing mechanisms in Petri nets.
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Fault injection techniques are increasingly used when designing a circuit, in order to analyze the potential cases in which a fault could lead to an application failure. In most experiments, such failures were simply defined as er...
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Fault injection techniques are increasingly used when designing a circuit, in order to analyze the potential cases in which a fault could lead to an application failure. In most experiments, such failures were simply defined as erroneous responses of the circuit. However, in many cases, an erroneous response does not necessarily lead to a failure at the application level, even when the discrepancy with the nominal behavior has a long duration. An accurate but high-level modeling of the complete system is therefore required to discriminate real failure conditions from non-critical errors. On the opposite, performing fault injections on a very high level modeling of the circuit functions does not allow a designer to analyze the effect of real faults potentially occurring in the field, such as bit-flips in internal registers. Injections must therefore be performed using a RT level (or lower level) modeling of the circuit, connected to the system-level modeling of the environment. This paper presents an approach for such mixed-level dependability analyses and reports on a case study.
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The problems of a noise analysis of nonlinear circuits for small and large signal levels are surveyed. It is shown, that the known method of correlation analysis of linear circuits requiring knowledge of the correlation matrices o...
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The problems of a noise analysis of nonlinear circuits for small and large signal levels are surveyed. It is shown, that the known method of correlation analysis of linear circuits requiring knowledge of the correlation matrices of all elements of the circuit can be implemented at a level of primary sources of noises of each circuit element. Such an approach essentially simplifies a mathematical and algorithmic realization of the analysis, dilating its possibilities on all devices, for which the equivalent noise circuits are known but the correlation noise matrix is not obtained. The nonlinear analysis of nonlinear circuit noise is discussed. The method of nonlinear noise analysis based on canonical decomposition of spectral densities of the circuit's noise sources is presented. The method, contrary to the LSSS method, widely used in the programs for the nonlinear analysis of microwave and RF circuits, allows effectively to parse both poorly "rustling" circuits, and circuit with a very high noise level, when the nonlinearity of the circuit in relation to noise cannot be neglected.
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Mixed-level device and circuit simulation allows the use of one- or two-dimensional numerical models for critical devices in a circuit configuration. CODECS is a mixed-level device and circuit simulator that has been developed to ...
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Mixed-level device and circuit simulation allows the use of one- or two-dimensional numerical models for critical devices in a circuit configuration. CODECS is a mixed-level device and circuit simulator that has been developed to support a variety of numerical models and analyses capabilities. Effective coupling of device and circuit simulation capabilities is achieved by a proper choice of algorithms and architecture. Several examples illustrate the advantages of CODECS for simulating both MOS and bipolar circuits.
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Transistor-level power simulators have been popularly used to estimate the power dissipation of a CMOS circuit. These tools strike a good balance between the conventional transistor-level simulators, such as SPICE, and the logic-l...
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Transistor-level power simulators have been popularly used to estimate the power dissipation of a CMOS circuit. These tools strike a good balance between the conventional transistor-level simulators, such as SPICE, and the logic-level power estimators with regard to accuracy and speed. However, it is still too time-consuming to run these tools for large designs. To simulate one-million functional vectors for a 50 K-gate circuit, these power simulators may take months to complete. In this paper, we propose an approach to generate a compact set of vectors that can mimic the transition behavior of a much larger set of functional vectors, which is given by the designer or extracted from application programs. This compact set of vectors can then replace the functional vectors for power simulation to reduce the simulation time while still retaining a high degree of accuracy. We present experimental results to show the efficiency and accuracy of this approach.
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摘要 :
Transistor-level power simulators have been popularly used to estimate the power dissipation of a CMOS circuit. These tools strike a good balance between the conventional transistor-level simulators, such as SPICE, and the logic-l...
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Transistor-level power simulators have been popularly used to estimate the power dissipation of a CMOS circuit. These tools strike a good balance between the conventional transistor-level simulators, such as SPICE, and the logic-level power estimators with regard to accuracy and speed. However, it is still too time-consuming to run these tools for large designs. To simulate one-million functional vectors for a 50 K-gate circuit, these power simulators may take months to complete. In this paper, we propose an approach to generate a compact set of vectors that can mimic the transition behavior of a much larger set of functional vectors, which is given by the designer or extracted from application programs. This compact set of vectors can then replace the functional vectors for power simulation to reduce the simulation time while still retaining a high degree of accuracy. We present experimental results to show the efficiency and accuracy of this approach.
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Time domain as opposed to frequency domain analysis is necessary in certain cases, for instance, to determine the effect of transients on non-linear systems. Time domain analysis methods however have the disadvantage of being sign...
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Time domain as opposed to frequency domain analysis is necessary in certain cases, for instance, to determine the effect of transients on non-linear systems. Time domain analysis methods however have the disadvantage of being significantly more complex and requiring much longer solution times than frequency domain analysis methods. Conventional methods for time domain -waveguide analysis include the finite difference time domain method and the method of moments. Intermediate level circuit modeling methods have been shown to be far more efficient than these conventional methods. A novel equivalent circuit of a waveguide section suitable for intermediate level circuit modeling is proposed that has the advantage of being easier and quicker to formulate, and requires significantly less time to reach a solution than conventional time domain methods. The time domain solution is arrived at by utilizing a circuit simulator (SPICE) to analyze the intermediate level circuit model, that uses the proposed equivalent circuit for waveguide sections. Results obtained using the proposed circuit in SPICE were found to be credible when compared to known analytical results.
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In this paper, we propose a novel hierarchical analysis methodology to facilitate efficient chip-level power fluctuation analysis. With extreme efficiency and simplicity, our design methodology first builds time-varying multiport ...
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In this paper, we propose a novel hierarchical analysis methodology to facilitate efficient chip-level power fluctuation analysis. With extreme efficiency and simplicity, our design methodology first builds time-varying multiport Norton equivalent circuits in a row-by-row or block-by-block basis, followed by global analysis of the integrated reduced models. After generating the Norton equivalent sources at external ports, we apply realizable model order reduction technologies to further reduce the model. Since the elements of our reduced model are also RC devices, they are fully compatible with general circuit simulation engines. The experimental results demonstrate more than 4/spl times/ speed up with the flat simulation while maintaining within 5% accuracy.
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Spatial power/ground level variation causes power/ground level mismatch between driver and receiver, and the mismatch affects gate propagation delay. This work proposes a timing analysis method based on a concept called "PG level ...
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Spatial power/ground level variation causes power/ground level mismatch between driver and receiver, and the mismatch affects gate propagation delay. This work proposes a timing analysis method based on a concept called "PG level equalization" which is compatible with conventional STA frameworks. We equalize the power/ground levels of driver and receiver. The charging/discharging current variation due to equalization is compensated by replacing output load. We present an implementation method of the proposed concept, and demonstrate that the proposed method works well for multiple-input gates and RC load models.
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摘要 :
Spatial power/ground level variation causes power/ground level mismatch between driver and receiver, and the mismatch affects gate propagation delay. This work proposes a timing analysis method based on a concept called "PG level ...
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Spatial power/ground level variation causes power/ground level mismatch between driver and receiver, and the mismatch affects gate propagation delay. This work proposes a timing analysis method based on a concept called "PG level equalization" which is compatible with conventional STA frameworks. We equalize the power/ground levels of driver and receiver. The charging/discharging current variation due to equalization is compensated by replacing output load. We present an implementation method of the proposed concept, and demonstrate that the proposed method works well for multiple-input gates and RC load models.
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